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ADE7880
Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled
by ±100% by writing to one of the phase’s PGAIN 24-bit
registers (APGAIN, BPGAIN, or CPGAIN). Note that these
registers are the same gain registers used to compensate the
Gain Calibration section for details on these registers.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
Data Sheet
registers. The content of these registers is transferred to the VA-
hour registers, xVAHR, when these registers are accessed.
VATHR 8-bit unsigned register concatenated to 27 bits equal to
0. It is introduced by the user and is common for all phase total
active and fundamental powers. Its value depends on how much
energy is assigned to one LSB of VA-hour registers. When a
derivative of apparent energy (VAh) [10 n VAh], where n is an
integer, is desired as one LSB of the xVAHR register, the
xVATHR register can be computed using the following equation:
(see the Root Mean Square Measurement section). The voltage
and current rms values are multiplied together in the apparent
power signal processing. As no additional offsets are created in
VATHR =
PMAX × f s × 3600 × 10 n
U FS × I FS × 2 27
(44)
the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The offset
compensation of the apparent power measurement in each phase is
accomplished by calibrating each individual rms measurement.
Apparent Power Calculation Using VNOM
The ADE7880 can compute the apparent power by multiplying
the phase rms current by an rms voltage introduced externally in
the VNOM 24-bit signed register.
When one of Bits[13:11] (VNOMCEN, VNOMBEN, or
VNOMAEN) in the COMPMODE register is set to 1, the
apparent power in the corresponding phase (Phase x for
VNOMxEN) is computed in this way. When the VNOMxEN
bits are cleared to 0, the default value, then the arithmetic
apparent power is computed.
where:
PMAX = 27,059,678 = 0x19CE5DE, the instantaneous power
computed when the ADC inputs are at full scale.
f S = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
U FS , I FS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
The VATHR register is an 8-bit unsigned number, so its
maximum value is 2 8 ? 1. Its default value is 0x3. Values lower
than 3, that is 2 or 1 should be avoided and 0 should never be
used as the threshold must be a non-zero value.
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
Equation 45.
ApparentEn ergy = ∫ s ( t ) dt = Lim ? ∑ s ( nT ) × T ?
The VNOM register contains a number determined by U, the
desired rms voltage, and U FS , the rms value of the phase voltage
when the ADC inputs are at full scale:
where:
? ∞ ?
T → 0 ? n = 0 ?
(45)
VNOM = × 3 , 766 , 572
U
U FS
(42)
n is the discrete time sample number.
T is the sample period.
where U is the nominal phase rms voltage.
As stated in the Current Waveform Gain Registers, the serial
ports of the ADE7880 work on 32-, 16-, or 8-bit words. Similar
to the register presented in Figure 57, the VNOM 24-bit signed
register is accessed as a 32-bit register with the eight MSBs
padded with 0s.
Apparent Energy Calculation
Apparent energy is defined as the integral of apparent power.
In the ADE7880 , the phase apparent powers are accumulated in
the AVAHR, BVAHR, and CVAHR 32-bit signed registers. The
apparent energy register content can roll over to full-scale
negative (0x80000000) and continue increasing in value when the
apparent power is positive. Conversely, if because of offset
compensation in the rms data path, the apparent power is
negative, the energy register underflows to full-scale positive
(0x7FFFFFFF) and continues to decrease in value.
The ADE7880 provides a status flag to signal when one of the
Apparent Energy = ∫ s ( t ) dt
(43)
xVAHR registers is half full. Bit 4 (VAEHF) in the STATUS0
Similar to active and reactive powers, the ADE7880 achieves
the integration of the apparent power signal in two stages (see
Figure 79). The first stage accumulates the instantaneous
apparent power at 1.024 MHz, although they are computed by
the DSP at 8 kHz rate. Every time a threshold is reached, a pulse
is generated and the threshold is subtracted from the internal
register. The second stage consists in accumulating the pulses
generated after the first stage into internal 32-bit accumulation
register is set when Bit 30 of one of the xVAHR registers changes,
signifying one of these registers is half full. As the apparent
power is always positive and the xVAHR registers are signed, the
VA-hour registers become half full when they increment from
0x3FFFFFFF to 0x40000000. Interrupts attached to Bit VAEHF in
the STATUS0 register can be enabled by setting Bit 4 in the MASK0
register. If enabled, the IRQ0 pin is set low and the status bit is
set to 1 whenever one of the Energy Registers xVAHR becomes
half full. The status bit is cleared and the IRQ0 pin is set to high
Rev. A | Page 54 of 104
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